A HIGH PERFORMANCE FULLY DIFFERENTIAL PURE CURRENT MODE OPERATIONAL AMPLIFIER AND ITS APPLICATIONS

In this paper a novel high performance all current-mode fully-differential (FD) Current mode Operational Amplifier (COA) in BIPOLAR technology is presented. The unique true current mode simple structure grants the proposed COA the largest yet reported unity gain frequency while providing low voltage low power operation. Benefiting from some novel ideas, it also exhibits high gain, high common mode rejection ratio (CMRR), high power supply rejection ratio (PSRR), high output impedance, low input impedance and most importantly high current drive capability. Its most important parameters are derived and its performance is proved by PSPICE simulations using 0.8 μm BICMOS process parameters at supply voltage of ±1.2V indicating the values of 82.4 dB,52.3º, 31.5 Ω, 31.78 MΩ, 179.2 dB, 2 mW and 698 MHz for gain, phase margin, input impedance, output impedance, CMRR, power and unity gain frequency respectively. Its CMRR also shows very high frequency of 2.64 GHz at zero dB. Its very high PSRR+/PSRR- of 182 dB/196 dB makes the proposed COA a highly suitable block in Mixed-Mode (SOC) chips. Most favourably it can deliver up to ±1.5 mA yielding a high current drive capability exceeding 25. To demonstrate the performance of the proposed COA, it is used to realize a constant bandwidth voltage amplifier and a high performance Rm amplifier

A Novel Fully Differential Second Generation Current Conveyor and Its Application as a Very High CMRR Instrumentation Amplifier

This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW.  Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits

An Offset-free High linear Low Power High Speed Four-Quadrant MTL Multiplier

In this paper a new CMOS current-mode four-quadrant analog multiplier circuit is proposed. The major advantages of this design are high linearity, high speed and low power consumption. Removing dc offset is the most important improvement in this topology. The circuit is designed with 1.8V supply voltage and is simulated using HSPICE simulator by level 49 parameters in 0.18µm standard CMOS TSMC technology. The aspect ratios of the MOSFETs are optimized using Evolutionary algorithm by MATLAB. The simulation results of this analog multiplier demonstrate a maximum linearity error of 2.6%, a THD of 1.77%, maximum power consumption of 157 µW, -3dB bandwidth of 241MHz and almost free from dc offset

Persian Registry Of cardioVascular diseasE (PROVE): Design and methodology

BACKGROUND: Our aim was to create and establish a database called &ldquo;Persian Registry Of cardioVascular diseasE (PROVE)&rdquo; in order to be used for future research and in addition, as a tool to develop national guidelines for diagnosis, treatment, and prevention of cardiovascular disease (CVD). In this paper, the design and methodology of the PROVE pilot study will be discussed, launched in Isfahan, Iran, in 2015-2016. METHODS: Through establishing PROVE, patients' data were collected from hospitals and outpatient clinics prospectively or retrospectively and followed up for a maximum of three years based on the type of CVDs. The inclusion criteria were as patients with acute coronary syndrome (ACS), ST elevation myocardial infarction (STEMI), stroke, atrial fibrillation (AF), heart failure (HF), congenital heart disease (CHD), percutaneous coronary intervention (PCI), and chronic ischemic cardiovascular disease (CICD). Specific protocols, questionnaires, and glossaries were developed for each registry. In order to ensure the validation of the protocols, questionnaires, data collection, management, and analysis, a well-established quality control (QC) protocol was developed and implemented. Data confidentiality was considered. RESULTS: In order to register patients with ACS, STEMI, stroke, HF, PCI, and CICD, the hospital recorded data were used, whereas, in case of AF and CHD registries, the data were collected from hospitals and outpatient clinics. During the pilot phase of the study in Isfahan, from March 2015 to September 2016, 9427 patients were registered as ACS including 809 as STEMI, 1195 patients with HF, 363 with AF, 761 with stroke, 1136 with CHD, 1200 with PCI, and 9 with CICD. Data collection and management were performed under the supervision of the QC group. CONCLUSION: PROVE was developed and implemented in Isfahan as a pilot study, in order to be implemented at national level in future. It provides a valuable source of valid data that could be used for future research, re-evaluation of current CVD management and more specifically, gap analysis and as a tool for assessment of the type of CVDs, prevention, treatment, and control by health care decision makers. &nbsp;&nbsp;</p